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Narendrajobs
Job Overview
DV and DFT Jobs
Experience: 5-20 Years
Location: PAN-INDIA
Notice Period: Immediate to 45 Days
Apply here
https://forms.gle/rCEuast71kmkBez99
DV
Role: IP/Sub-System Verification
Experience : 5 to 20 yrs
Notice Period : immediate to 45 days
Positions : 20
Job Description:
- Working experience in System Verilog and OVM/UVM methodologies. (UVC creation, integration, SV coverage, SV assertions, SV constraints, UVM sequences etc)
- Should have IP/Sub-System level verification experience.
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- Develop verification plan, Build complex test-bench environments and identifying corner case scenarios, exposing Arch/corner case bugs and closing coverage
- Experience with coverage driven verification methodologies.
- Experience with High Speed Interfaces- USB, DP/eDP, PCIE, DSI, CSI,
- Knowledge in AMBA bus protocols APB, AHB & AXI
- Experience with creating & working with Scalable and Reusable test-bench.
- Must have excellent knowledge of ASIC Verification Flow
- Excellent debug and problem solving skills ( Should be able to reach to root-cause issues)
- Familiarity with scripting languages likes Perl, Python
- Bug tracking – JIRA/CQ
- Experience on any revision tracking tool – Perforce, SVN, CVS
- Team player, can-do attitude is desirable
- Good communication skills.
Role & Responsibilities
- Understanding the Domain, Architecture, Specifications and Design.
- Contribute in developing verification strategy and verification environment architecture.
- Creation of Verification/Test plan.
- Creation of TB and TB components – BFM, Drivers, Checker, Monitors, Coverage Grids, Score-boards and reference models.
- Creation of reusable test cases and sequence library using directed random stimulus
- Setting up of compile and elaboration flow, regression engine, test-lists etc. .
- Verification of features/sub-features of the design and debug of failures.
- Running/Managing Regressions and clean-up of regression failures.
- Functional and code coverage closure
- Supporting the SOC team and resolving issues/ queries related to the IP.
- Re-usability/Scalability of the test-bench
- Working with and helping other team members
Role: SoC Verification
Experience : 5 to 20 yrs
Notice Period : immediate to 45 days
Positions : 20
Job Description:
- Good understanding of Arm Based SoCs
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- SoC Bus backbone ( ARM NIC, CCN, Bridges, DRAM memory controllers and cache coherency concepts)
- SoC bus components like MMU, Quality Enhancer.
- Good understanding of SoC Power Management and Clock management.
- Experience in at least ONE of these blocks: Amba, Bus Interconnect, Memory interface ( DRAM and LPDDR4 ), PCIE, Ethernet, CAN, UFS, eMMC , Camera MIPI CSI/DSI, DP, ISP, USB, Security Subsystem including ARM TrustZone, GPU, Audio, Video, ARM CPU and Design For Debug ( DFD), peripherals interfaces – UART, I2C, I2S, SPI, flash memory interfaces verification at sub-system/Full-chip level.
- Experience with SOC Bus protocols: AMBA Bus interfaces (AXI, AHB, APB) and/or OCP highly desirable.
- Must have excellent knowledge of ASIC Verification Flow
- Experience with current verification methodologies (UVM, OVM, VMM, Specman, …)
- Should have SoC level verification experience. ( Build complex testbench environments and identifying corner case scenarios and exposing Arch/corner case bugs)
- Experience in power aware and Low Power management verification.
- Experience in Performance Verification with Emulators is plus.
- Experience with coverage based verification methodologies.
- Excellent debug skills in both functional ( Should be able to Rootcause the issue)
- Familiarity with scripting languages likes Perl, Phython
- Experience with setting up and running gate level simulations
DFT
Role: Team Lead – DFT
Experience : 10+ Years
Notice Period : immediate to 45 days
Positions : 5
Job Description:
Should have worked hands-on extensively on full chip DFT design,
- Implementation, vector generation/verification, JTAG, boundary scan and simulation.
- Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus.
- Should have participated in successful tapeouts ofSoC/ASIC chips at 40nm or below and achieved test targets.
- Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.
- Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
- Excellent problem solving and debugging skills. Proactive in nature
- Leading junior teams, Mentoring/Training and Project leadership.
- Excellent Customer interaction, Communication and Team work skills
Qualification: BE/B.Tech in ECE /M.Tech in VLSI .
Role: Sr.DFT Engineer
Experience : 5+ Years
Notice Period : immediate to 45 days
Positions : 20
Job Description:
- Has worked on scan-stitching; and has good knowledge of scan-stitching related concepts..
- Has worked on MBISTBISR implementation and is confident with the Tessent flow of mbist-insertion..
- Has worked on ATPG; and is well conversed with the files required to run ATPG.. Knowledge experience with Tessent ATPG (mentor) is a plus
- Has worked on Spyglass-Lint.
- Knowledge on automation scripts is a plus..
- Knows the basics of JTAG & IJTAG.
- Support Spyglass debug and coverage co-relation.
- Support scan-stitching runs.. Debug DRC other scan-related issues
- Support ATPG.. debug ATPG issues.. debug coverage holes.
- Support MBISTBISR insertion.. debug insertion issues verification issues.
- Support gate-level simulations.
Qualification: BE/B.Tech in ECE /M.Tech in VLSI
Job Detail
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Experience5-20 Years
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